1. Field of the Invention
The present invention relates to a memory cell layout structure for a semiconductor memory device. More specifically, the present invention relates to a layout structure of memory cells in which element isolating regions between adjacent memory cells can be minimized, enabling highly dense layout, in a dynamic random access memory (DRAM).
2. Description of the Background Art
In a DRAM, generally, one memory cell consists of one capacitor and one switching transistor, the amount of charges stored in the capacitor are associated with "0" and "1", and thus information is recorded. When the information is to be read, potential difference between a bit line to which the memory cell to be read is connected and another bit line to which a dummy cell is connected is differentially amplified by a sense amplifier. However, since slight change in potential appearing on the bit line connected to the capacitor must be detected, the influence of external noise to the bit lines must be minimized.
As a method of eliminating external noise to the bit lines, the following method is believed to be most effective and common, Namely, a so called folded bit line structure including a plurality of bit lines arranged parallel to and adjacent to each other and sense amplifiers provided at one end of the bit lines is used, so as to set most of the noises in in-phase mode, whereby the noises are offset with each other.
FIG. 1 is a schematic diagram showing memory cells and peripheral circuitry connected to such folded bit lines. Referring to FIG. 1, bit line pair 1a and 1b are arranged orthogonal to word lines 21 to 24, a memory cell MC1 is connected at a crossing between bit line 1a and word line 21, a memory cell MC2 is connected at a crossing between bit line 1b and word line 22, a memory cell MC3 is connected at a crossing between bit line 1a and word line 23, and a memory cell MC4 is connected at a crossing between bit line 1b and word line 24. Each of the memory cells MC1 to MC4 consists of one MOS transistor and one capacitor. Bit line pair 1a, 1b is connected to a bit line equalizing and precharging circuit 3, a sense amplifier 4 and transfer gates 51 and 52. Bit line equalizing and precharging circuit 3 precharges potentials of bit line pair 1a and 1b, sense amplifier 4 amplifies potential difference from any of the memory cells MC1 to MC4 read to the bit line pair 1a, 1b, and the information is output to an I/O line pair 6 through transfer gates 51 and 52.
FIG. 2 shows a layout of the memory cells in the conventional DRAM shown in FIG. 1. Referring to FIG. 2, word lines 21, 22, . . . are provided orthogonal to folded bit line pair 1a, 1b, memory cells MC1 and MC3 are arranged along bit line 1a, and memory cells MC2 and MC4 are arranged along bit line 1b. The MOS transistor of memory cell MC3 is connected to bit line 1a at a bit line contact 7. Capacitors 8a and 8b are formed at an upper layer of memory cell MC3 to storage contacts. In such memory cell layout, memory cells MC1 and MC3 are arranged spaced by a prescribed distance along bit line 1a, and memory cells MC2 and MC4 are arranged along bit line 1b shifted from memory cells MC1 and MC3 by one half the distance between centers of memory cells MC1 and MC3. However, in such an arrangement, element isolating region between adjacent two memory cells is considerably large, resulting in wasteful area 9, which leads to lower degree of integration.
There is another disadvantage in forming the bit line pair. Namely, it is difficult to provide folded bit lines while size of the memory cells are minimized and memory cells are laid out without wasteful region left between adjacent memory cells. In order to solve the above described problems, a semiconductor device having the following layout has been proposed.
FIG. 3 is a plan view of a semiconductor memory device disclosed in Japanese Patent Laying-Open No. 5-41500. In the example shown in FIG. 3, a pair of adjacent bit lines 1a and 1b are arranged separately in two electrically insulated layers, enabling formation of folded bit line structure which could not be implemented by the conventional single layered bit line structure. Accordingly, element isolating region between adjacent memory cells can be minimized, and highly integrated memory cells can be obtained without such a wasteful region 9 as shown in FIG. 2.
However, if such a layout as shown in FIG. 3 is employed, in forming bit lines, the number of manufacturing steps would be doubled as compared with formation of bit lines in only one layer, as the bit lines are formed into electrically insulated separate layers. In other words, the manufacturing process would be complicated. Further, since bit lines are formed in two separate layers electrically insulated from each other, formation of contact holes become more difficult as compared with the bit lines formed in one layer.
Further, at portions where bit lines are overlapped partially with each other with an interlayer insulating film interposed, bit line capacitance is increased, causing delay in circuit operation.